November 18, 2022
Editor’s Note: This content is republished from the MicroZed Chronicles, with permission from the author.
A few months ago, we looked at the AXI Stream FIFO. The AXI Steaming FIFO allows developers to be able to access AXI Streams from AXI memory mapped peripherals without the need to implement a full DMA solution.
Recently I have been working with a client on an image processing system, where the image data was received in a non-AXI format of line, data, frame valid signals and required the transition into AXIS for downstream processing.
This video format can be made into an AXI Stream simply but it can’t be stalled because the data is coming straight from the image sensor itself. I used an AXI-Stream Data FIFO to do this. As the name says, this is a FIFO which can be used to buffer AXIS data. In the case of the example I gave earlier, correctly sizing the FIFO enables the image data to be written to a buffer in an AXI Stream format without needing to apply back pressure. Of course, the FIFO needs to be sized correctly to achieve this. I sized the buffer at twice the line length because each video was 1024 pixels and the downstream element would be reading the data out.
The AXI Stream Data FIFO is an interesting component. When we work with AXI Streams, we often use the sideband signals such as TLast in addition to the core signals. We use these especially in image processing systems to indicate the start of a frame, end of line etc. It is crucial that these are also buffered in the FIFO since as they contain critical information.
Like with any FIFO, the AXI Stream Data FIFO can provide clock domain crossing from one domain to another.
Another interesting ability for secure or safety-critical designs is the ability to enable ECC on the memories used within the FIFO.
The AXI Stream DATA FIFO can operate in two modes. In normal mode, data is written into the slave mode and can be accessed via the master interface. In packet mode, the data is not available on the master interface until the TLast signal is received, signalling the end of a packet.
I created a simple test in Vivado which tested the FIFO in both modes.
Looking at the Vivado simulation, when the AXI Stream Data FIFO is configured for normal operation, you can see video frames running through the FIFO (I tied off Master TReady for simulation).
Each TValid period shows a line of video being written into the FIFO.
By zooming in on the start of the frame and the end of the line, we can see the TUser and TLast flowing through the FIFO as desired.
With packet mode enabled, we see a slightly different behavior and see the output data being delayed until the TLast is received.
Looking more in detail on the timing between the assertion of TLast on the slave input in the packet mode we can see the delay in data being passed through.
When working in packet mode, we need to be careful of the depth of the FIFO because we must be able to hold one full packet before it is output. Of course, data will also be in the process of being written into the FIFO as the data is being output. If we are working with a high-speed input which cannot be stalled, we need to size the FIFO appropriately to ensure that we do not result in the AXI Stream Data FIFO being full.